Ogras wins best paper award at Embedded Systems Week and receives Intel funding

Umit Y. Ogras, the Gene Amdahl Professor in electrical and computer engineering at the University of Wisconsin-Madison, received the best paper award at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), part of Embedded Systems Week held in Raleigh, North Carolina, in late September and early October 2024.

The winning paper is titled “A dataflow-aware network-on-interposer for CNN inferencing in the presence of defective chiplets.”  The paper’s co-authors from the Washington State University School of Electrical Engineering and Computer Science include lead author and PhD student Harsh Sharma and Professors Ananth Kalyanaraman and Partha Pande.

Chiplet-based architectures have emerged as promising alternatives to traditional monolithic 2D chips due to their lower fabrication costs. Compared to conventional monolithic systems, chiplet-based systems integrate multiple small, prefabricated chips (chiplets) on a silicon interposer, facilitating data exchange.

Ogras and his WSU collaborators have been working on multiple aspects of chiplet-based architectures, including communication-aware network-on-package (aka network-on-interposer) optimization, thermal modeling and management, and optimally mapping deep learning workloads on these architectures. 

Their winning paper proposes innovative methods to partition and maintain high performance even when dealing with defective chiplets. This multi-objective optimization approach significantly enhances performance, reduces energy consumption, and lowers fabrication costs.

Embedded Systems Week is the premier event covering all aspects of hardware and software design for intelligent and connected computing systems. It brings together three leading conferences (CASES, CODES+ISSS, EMSOFT), one symposium (MEMOCODE), and several workshops, tutorials, and education classes. CASES is a premier forum for researchers, developers, and practitioners in compilers and architectures for high-performance, low-power embedded systems.

The team has also received industrial funding support from Intel Corporation to continue and expand this research in two directions. A new sponsored project led by Ogras will investigate scalable and general methodologies for power-thermal modeling and management of chiplet architectures. The first goal is to demonstrate less than 5% modeling error with at least three orders of magnitude speedup against Finite Element Methods. Then, these models will be used to develop novel runtime power and thermal management techniques for architectures with 64 or more chiplets. 

Integrating several PEs or chiplets in a single system introduces additional data exchange. This data traffic necessitates the design and optimization of the interconnection network, which is the communication backbone of the 2.5D/3D chiplet system. This on-chip data exchange is exacerbated specifically for emerging machine learning applications. A second project will be led by Pande at Washington State University in collaboration with Ogras to tackle these communication challenges.