Zhewen Pan wins honorable mention at ISCA

A paper authored by Zhewen Pan, a PhD student in computer engineering at the University of Wisconsin-Madison, was chosen for an honorable mention at the International Symposium on Computer Architecture (ISCA) held in late June, 2025, in Tokyo, Japan.

ISCA is one the premier conferences in computer architecture, and selection as a best paper finalist is a prestigious honor in the field.

Pan’s paper, co-authored with her advisor Joshua San Miguel, an associate professor of electrical and computer engineering, is titled “The XOR Cache: A Catalyst for Compression.”

Modern computers utilize memory caches to help make processing faster and more efficient. But as computing needs have increased, caches have grown bigger, taking up significant portions of computer chips. Large caches, however, can often lead to slower performance.

The same data is usually cached in different levels of the computing process, called cache hierarchy. In her paper, Pan discusses a technique called XOR Cache to optimize the cache hierarchy, reducing the cache footprint and power use while maintaining performance. In essence, XOR Cache finds and reduces the amount of data redundancy throughout the cache hierarchy, improving efficiency.

San Miguel says this award is particularly gratifying. “The computer architecture community is growing widely right now towards more exotic topics, like AI security and quantum computing,” he says. “It’s actually surprisingly rare to the see this sort of traditional, old school, level of computer architecture recognized. But it’s applicable to any of these systems, and it’s the kind of thing you could potentially see in a textbook a few years from now.”

Featured Image: Zhewen Pan presents her paper at ISCA 2025 in Tokyo, Japan.