April 30
@
12:00 PM
–
1:00 PM
4610 Engineering Hall
Evolution of Manycores to Many Chiplets: A story of two decades
Professor Partha Pande
Boeing Centennial Chair in computer engineering at the school of Electrical Engineering and Computer Science
Washington State University
ECE is excited to welcome Professor Partha Pande, Boeing Centennial Chair in computer engineering at the school of Electrical Engineering and Computer Science, Washington State University.
The Chips and Science Act is opening new opportunities in microelectronics research and workforce generation. A multitude of governmental and industrial efforts in semiconductor research are initiated, providing unprecedented opportunities for academic research, university/industry partnerships, and educational initiatives. With almost two decades of experience in manycore heterogeneous architectures and 3D chip design in his group, Pande and others are in an advantageous position to tackle the challenges associated with technology scaling and heterogeneous integration. In this talk, Pande will first provide an overview of research on various aspects of heterogeneous manycore computing platforms enabled by the Network-On-Chip (NoC) paradigm that represents a powerful alternative to the data center-oriented type of computing. Next, he will emphasize on the interplay between machine learning and manycore systems. He will elaborate on how their work enables a virtuous cycle of ML techniques for advancing hardware designs spanning from edge devices to the cloud, which will empower further advances in ML (a.k.a. ML for ML). Following this, Pande will present their recent work on the emerging 2.5D chiplet platforms that provide a new avenue for compact scale-out implementations of various data- and compute-intensive workloads. Integrating multiple small chiplets using a Network-on-Interposer (NoI) offers not only significant cost reduction and higher manufacturing yield than 2D ICs but also better energy efficiency and performance. He will conclude this presentation by summarizing his work that encompasses the evolution of NoC-enabled manycore to NoI-based many chiplets architectures.
Bio:
Partha Pratim Pande is a professor and holder of the Boeing Centennial Chair in computer engineering at the school of Electrical Engineering and Computer Science, Washington State University, Pullman, USA. He is currently the Interim dean of the Voiland College of Engineering and Architecture (VCEA). His current research interests are novel interconnect architectures for manycore chips, on-chip wireless communication networks, heterogeneous architectures, and ML for EDA. Dr. Pande currently serves as the Editor-in-Chief (EIC) of IEEE Design and Test (D&T). He is on the editorial boards of IEEE Transactions on VLSI (TVLSI) and ACM Journal of Emerging Technologies in Computing Systems (JETC). He was the technical program committee chair of IEEE/ACM Network-on-Chip Symposium 2015 and CASES (2019-2020). He also either serves or served on the program committees of many reputed international conferences. He has won the NSF CAREER award in 2009. He is the winner of the Anjan Bose outstanding researcher award from the college of engineering, Washington State University in 2013. He is a fellow of IEEE. He has won 7 best paper awards and 5 more best paper award nominations.